1 mitsubishi digital assp ? M66305AP/afp toggle line buffer mitsubishi digital assp ? M66305AP/afp toggle line buffer description m66305a toggle line buffer has two 5,120-bit line buffer memories. it takes in serial data that arrives synchronously with clock pulses and outputs it in serial at a rate of up to 10 mbits per second synchronously with external clock pulses. this buffer employs the double buffer system: while data is being output, data on the next line can be written on the other line buffer memory. features ? 5,120 1bit serial input-serial output line buffer memories ? data transmission at 10 megabits/second maximum ? two line buffer memories can be alternated by external toggle signal. ? memory capacity can be doubled by cascade connection. ? because of cascade input pin (cas1), output potential after completion of output can be set to either h or l. ? low noise and high fan-out output (i o = 24ma guaranteed) ? every input pin has built-in schmidt trigger circuit. ? read counter and write counter can be reset independently. ? reset, t, cntrst1 and cntrst2 are equipped with negative noise reduction circuit. application data buffer between industrial or home-use image data pro- cessing system and peripheral equipment pin configuration (top view) block diagram t ice siclk sidata cas1 cntrst2 cntrst1 reset cs int oce soclk sodata bf toggle signal input input clock enable input clock input data cascade input 1 read counter reset input write counter reset input reset input chip select input write request output output clock enable output clock output data buffer full output matching detection circuit read counter write register write counter switch and p.g. address selector 5120 bits 5120 bits a d d i d 0 a d d i d 0 toggle f/f data selector data buffer wr wr s-ram s-ram 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 gnd siclk sidata ice cas1 gnd t cs reset gnd v cc sodata soclk oce cas2 cntrst2 cntrst1 v cc bf int input clock input data input clock enable cascade input 1 toggle signal input chip select input reset input output data output clock output clock enable cascade input 2 read counter reset input write counter reset input (5v) buffer full output write request output outline 20p4 outline 24p2w-a nc: no connection m66305afp M66305AP gnd siclk sidata ice cas1 nc nc gnd t cs reset gnd v cc sodata soclk oce cas2 nc nc cntrst2 cntrst1 v cc bf int input clock input data input clock enable cascade input 1 toggle signal input chip select input reset input output data output clock output clock enable cascade input 2 read counter reset input write counter reset input (5v) buffer full output write request output
2 mitsubishi digital assp ? M66305AP/afp toggle line buffer eration is switched to read mode, and the line buffer which has completed output is switched to write mode, enabling next write and read operations. to rewrite data during write operation, use write counter re- set input (cntrst1). to repeat output during output opera- tion, use read counter reset (cntrst2). these operations are possible only when the status of chip select (cs) is l. function when the status of input clock enable (ice) is l, input data (sidata) is taken in (written) synchronously with input clock (siclk) rise edge. when output clock enable (oce) is l, output data (sodata) is output (read) synchronously with output clock (soclk) fall edge. the double buffer system makes independent read and write operation possible. when one-line write and one-line read are completed, toggle signal (t) is required to be changed to l, with input of toggle signal, the line buffer memory which has completed write op- function table res l h h h h h h h h h h h ice x x h l h l l h l h x x cs x h l l l l l l l l l l sic x x x x l x l x x x oce x x h h l l x x x x l h soc x x x x l l x x l x t x x h h h h h h h h cr1 x x h h h h h h h h cr2 x x h h h h h h h h sod l q 0 q 0 q 0 *2 *2 *4 *5 *6 int h q 0 q 0 q 0 *3 *3 h *5 h bf h q 0 q 0 *1 q 0 *1 h h *6 remarks initialization no internal change, no output change no internal change, no output change with rise of siclk, data is written on line buffer memory. with fall of soclk, data is output. write and read with rise of t: 1) line buffer memory in read mode is switched to write mode and the other in write mode is switched to read mode. 2) bf and int are canceled. with cntrst1 input, internal write counter is reset, enabling rewriting. with cntrst2 input, internal read counter is reset, enabling retrial of output. output input q 0 : no change x : h or l *1 : bf changes from h to l with rise of siclk for write of 5120th bit. *2 : with fall of soclk, data written before toggle signal input is output in order. *3 : int changes from h to l when the status of soclk rises after output of final bit of written before toggle signal inputs. *4 : outputs the first bit of written data (d 0 ). *5 : output operation can be performed irrespective of cntrst1. *6 : sodata changes to the first bit of written data (d 0 ). write operation can be performed irrespective of cntrst2.
3 mitsubishi digital assp ? M66305AP/afp toggle line buffer functions initializes integrated circuit. (sodata =l, bf =h, int = h) l: chip select h: non-select (inputs other than reset have no effects on circuit inside.) l: input clock (siclk) enable h: input clock (siclk) disable with rise of siclk, sidata is written on line buffer memory. l: output clock (soclk) enable h: output clock (soclk) disable with fall of soclk, sodata is output. because buffer is provided between memory and output, each piece of data is propagated at a constant rate, irrespective of internal memory read access time. the line buffer memory in write mode is switched to read mode, and the other in read mode is switched to write mode. output when siclk rises for input of 5,120th bit, indicating no more writing is possible. when bf is l, circuit inside is automatically set to input disable. bf is canceled with rise of toggle signal (t) status. output when soclk rises after output of final bit of written data. when int is l, circuit inside is automatically set to output disable. int is canceled with rise of toggle signal (t) status. used to rewrite data during write operation when cs is l. used to undo data output halfway or to retry output when cs is l. output when soclk falls after output of final bit of written data. when cascade connection is not used, be sure to connect this pin to v cc or gnd. up to 2 cascade connections are possible. connect the ca2 pin of master ic to v cc , and the ca2 pin of slave ic to gnd. refer to application example for details. non-connected pin provided only for m66305afp. this pin can be used for wiring. pin description name reset input chip select input input clock enable input clock input data output clock enable output clock output data toggle signal input buffer full output write request output write counter reset input read counter reset input cascade input 1 cascade input 2 no connection pin reset cs ice siclk sidata oce soclk sodata t bf int cntrst1 cntrst2 cas1 cas2 nc
4 mitsubishi digital assp ? M66305AP/afp toggle line buffer basic timing diagram * circuit operates as shown in this timing chart in case one line length 5,120. if the line length is shorter than this, bf stays h status. operation flowchart during the first cycle of operation after reset, write operation is possible but read operation is impossible. input toggle sig- nal (t) after the one-line data is written. during the second and following cycles, the previous written data can be output or new data can be written in parallel. af- ter one-line data is written and output is completed (int out- put), input toggle signal (t). reset write operation completion? toggle signal write operation output operation write completion and int detection? completion? end start yes no yes no yes no ice siclk sidata bf t oce soclk sodata int d0(a) d1(a) d5118(a) d5119(a) cas1 d0(b) d0(b) d1(b) d2(b) d5118(b) d5119(b) d0(c)
5 mitsubishi digital assp ? M66305AP/afp toggle line buffer conditions mounted ratings C0.5 ~ +7.0 C0.5 ~ v cc + 0.5 C0.5 ~ v cc + 0.5 700 C65 ~ 150 symbol v cc v i v o p d t stg parameter supply voltage input voltage output voltage power dissipation storage temperature unit v v v mw c absolute maximum ratings recommended operational conditions (t a = C10?c ~ 70 c unless otherwise noted) symbol v cc gnd v i v o t opr parameter supply voltage supply voltage input voltage output voltage operating ambient temperature limits min. 4.5 0.0 0.0 C10 typ. 5.0 0.0 max. 5.5 v cc v cc 70 unit v v v v c conditions symbol v t+ v tC v t+ - v tC v oh v ol i cc i ih i il c i parameter positive threshold voltage negative threshold voltage hysteresis width h output voltage l output voltage quiescent supply current h input current l input current input capacitance electrical characteristics (t a = C10?c ~ 70 c, v cc = 5v 10% and gnd = 0v unless otherwise noted) max. 2.4 0.53 130 110** +1.0 C1.0 10 unit v v v v v ma m a m a pf typ. 0.4 v cc C0.35* v cc C0.4** 0.25* 0.30** 55* 45** min. 0.6 v cc C 0.8 limits test conditions all input i oh =C24ma i ol =+24ma v i =v cc or gnd v i =5.5v v i =0v the current flowing into the ic is positive current. *ta=25?c **ta=70?c
6 mitsubishi digital assp ? M66305AP/afp toggle line buffer symbol t w (sic) t w (soc) t w(t) t w(res) t w(cr1) t w(cr2) t su(sid-sic) t h(sic-sid) t su(ice-sic) t h(sic-ice) t su(cs-sic) t h(sic-cs) t su(oce-soc) t h(soc-oce) t su(cs-soc) t h(soc-cs) t su(cs-t) t h(t-cs) t h(sic-t) t rec(t-sic) t h(soc-t) t rec(t-soc) t su(cs-cr1) t h(cr1-cs) t su(cs-cr2) t h(cr2-cs) t rec(r-sic/soc) t rec(cr1-sic) t rec(cr2-soc) parameter input clock pulse width (note 2) output clock pulse width (note 2) toggle signal input pulse width reset input pulse width write counter reset input pulse width read counter reset input pulse width input data setup time before input clock input data hold time after input clock input clock enable setup time before input clock input clock enable hold time after input clock chip select setup time before input clock chip select hold time after input clock output clock enable setup time before output clock output clock enable hold time after output clock chip select setup time before output clock chip select hold time after output clock chip select setup time before toggle signal input chip select hold time after toggle signal input toggle signal hold time after input clock input clock recovery time after toggle signal input toggle signal hold time after output clock output clock recovery time after toggle signal input chip select setup time before write counter reset chip select hold time after write counter reset chip select setup time before read counter reset chip select hold time after read counter reset input and output clock recovery time after reset input clock recovery time after write counter reset output clock recovery time after read counter reset timing conditions (t a = C10?c ~ 70 c, v cc = 5v 10% and gnd = 0v unless otherwise noted) max. unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns typ. min. 30 43* 50 150 100 100 100 25 0 25 0 150 100 25 0 150 100 100 100 100 150 100 150 100 100 100 100 100 150 150 limits note 2 to satisfy switching characteristic f max = 10 mhz (frequency: 100ns), the condition shown below should be met: 100 ns (t w+ ) + (t wC ) symbol tc (sic) tc (soc) t plh(soc-sod) t phl(soc-sod) t phl(sic-bf) t phl(soc-int) t plh(t-bf) t plh(t-int) t plh(r-bf) t plh(r-int) t phl(cr1-bf) t plh(cr2-int) parameter input clock cycle time output clock cycle time propagation time between input clock and output data propagation time between input clock and bf propagation time between output clock and int propagation time between toggle signal input and bf propagation time between toggle signal input and int propagation time between reset input and bf propagation time between reset input and int propagation time between write counter reset and bf propagation time between read counter reset and int switching characteristics (t a = C10?c ~ 70 c, v cc = 5v 10% and gnd = 0v) max. 36 40 36 40 75 85 75 85 100 100 100 100 100 100 unit ns ns ns ns ns ns ns ns ns ns ns ns typ. min. 100 100 limits test conditions c l =50pf c l =150pf c l =50pf c l =150pf c l =50pf c l =150pf c l =50pf c l =150pf c l =150pf note 3 ac test waveform ; input pulse level: 0v ~ 3v input pulse rise time: 6ns *: ta=25?c input pulse fall time: 6ns test voltage ; input voltage: 1.3v output voltage: 1.3v
7 mitsubishi digital assp ? M66305AP/afp toggle line buffer timing charts ice siclk sidata sodata cs ice siclk cs oce soclk t h(soc-cs) t h(soc-oce) t w+(soc) t su(oce-soc) t su(cs-soc) t w-(soc) t plh(soc-sod) t phl(soc-sod) t su(ice-sic) t h(sic-ice) t h(sic-sid) t su(sid-sic) t w-(sic) t su(cs-sic) t w+(sic) t su(ice-sic) t h(sic-ice) t h(sic-cs) (note 4) note 4. timing to invalidate the clock. t c(sic) t c(soc)
8 mitsubishi digital assp ? M66305AP/afp toggle line buffer oce t su(oce-soc) t h(soc-oce) t su(cs-t) t w(t) t h(t-cs) t su(cs-cr1) t w(cr1) t h(tr1-cs) t su(cs-cr2) t w(cr2) t h(tr2-cs) soclk sodata cs t cs cs cntrst1 cntrst2
9 mitsubishi digital assp ? M66305AP/afp toggle line buffer int siclk /soclk bf t reset /cntrst1 /cntrst2 siclk /soclk int bf t h(sic-t) t h(soc-t) t rec(t-sic) t rec(t-soc) t phl(soc-int) t phl(sic-bf) t plh(t-bf) t plh(t-int) t w(res) t rec(res-sic)/(res-soc) t rec(cr1-sic) t rec(cr2-soc) t plh(res-bf)/(cr1-bf) t plh(res-int)/(cr2-int)
10 mitsubishi digital assp ? M66305AP/afp toggle line buffer application example note 5. output clock recovery time after toggle signal input [t re(t-soc) : 1) when one line length is 5,125 bits (5,120 +5) or less, t rec(t-soc) is required to be 500 ns or more. 2) when one line length is 5,126 bits (5,120 +6) or more, t rec(t-soc) is required to be 150 ns or more. note 6. ics used in this example connection: m66305a: 2pcs. m74hc32: 1pc. gnd siclk sidata ice cas1 gnd t cs reset gnd v cc sodata soclk oce cas2 cntrst2 cntrst1 v cc bf int gnd siclk sidata ice cas1 gnd t cs reset gnd v cc sodata soclk oce cas2 cntrst2 cntrst1 v cc bf int siclk sidata ice t reset sodata soclk v cc cntrst2 cntrst1 oce gnd bf int cs cas1 (v cc or gnd)
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